The present invention relates to an address generating unit within a DMA controller.
The conventional address generating unit, using a base address and a word length as parameters, generates addresses through addition or subtraction between an output from a word counter and the base address.
The address generating unit having such a construction has a problem that the generated addresses are always successive and skipped addresses can not be generated.
This is not problematic in the case where data to be transferred are always mapped on a memory so that they are successively accessed in the ascending or descending order thereof. However, in inter-processor communications through complicated networks, etc., data sources (transmitter) and data destinations (receivers) are not necessarily fixed. In many cases, certain collected data are not stored in successive memory regions but the respective data are stored at certain regularly skipped addresses. In this case, if the data are accessed through the conventional manner, disadvantages such as a necessity of rewriting the value of a register storing a base address whenever one word is accessed will be encountered, thereby extremely greatly reducing the efficiency of the address generating unit.